10 Gbit/s to 10 Tbit/s Non-blocking Ethernet switching shelves with 100 ms buffers for Carrier Ethernet, Enterprise and Data Center networks
Dune Networks, a provider of networking devices for Metro Ethernet, Enterprise and Data Center platforms, announced the availability of its PETRA line of FAP (Fabric Access Processor) devices as part of its SAND chipset. Announced are the P220 and P230 devices of the Petra family, providing 40Gbits/s and 80Gbits/s full-duplex traffic management and fabric access functionality. By quadrupling the level of integration of existing devices in the market today, the P220 and P230 drive the evolution toward dense 10GE-port systems. The P220 and P230, together with the new generation of classification devices, enable the economic design of nonblocking switches with deep buffering and densities of hundreds of 10GE ports in a single shelf. The devices further support 40GE or OC768c rate ports and are ready of 100GE port rate.
The PETRA family enables system vendors building a product-line to share the same switching and traffic management infrastructure, and to address both different densities and different applications. Cost effective small chassis can be designed by meshing several P220/P230 devices without the need of fabric devices/cards. Half rack chassis with densities of hundreds of 10GE ports can be designed by interconnecting the P220/P230 with fabric element devices. Multiple chassis of different sizes can be interconnected in a non-blocking resilient way via multi-stage fabric organization, supporting a world record of over 100Tbps of line rate capacity or thousands of 10GE ports or 40GE/100GE equivalent.
System vendors which are shipping in volume switching platforms based on earlier generations of SAND devices (e.g. FAP10V/20V/11V/21V FE200) are able to enhance their deployed switching systems. New line cards with higher 10GE ports density or supporting 40GE/OC768c port rates can be plugged into the legacy deployed systems. The P220 and P230 maintain Dune’s backward compatibility methodology extending product life-cycle to more than 10 years.
“Dune’s P220 and P230 devices strengthen Dune’s leading position in the switch market”, said Jag Bolaria, Senior Analyst with The Linley Group. “On the basis of availability, nonblocking performance, integration, and scalability, Dune’s P220 and P230 represent the leading fabric and TM architecture as well as being the first 80G full-duplex devices to sample. We believe the PETRA family should enable Dune’s customers to target new applications and reduce development time.”
“We are excited to release the new PETRA family, and drive switching and traffic management to the next level of speeds and HQoS requirements,” said Eyal Dagan, Chief Executive Officer of Dune Networks. “The P220 and P230 join the previous generations of SAND chipset that are employed in over 100 designs and are accelerating the mass adoption of 10GE in the enterprise, data center, and carrier networks”.
The P220/P230 in more detail:
The PETRA P220 and P230 support multiple interfaces on the line side enabling the connection of a wide range of Network Processors, Packet Processor devices, and FPGA devices. The P220 and P230 provide DRAM-based, deep packet buffering, which enables comprehensive traffic management, and integrate an interface that facilitates a Clos mesh fabric interconnect.
The PETRA devices support a wide range of line interfaces, including XAUI, XAUI+, SPAUI, RXAUI, SGMII, and SGMII+. XAUI+ doubles the data rates up to 6.25Gbits/s; RXAUI is like XAUI, but using two lanes running at 6.25Gbits/s; SGMII+ is like SGMII, but runs at 2.5Gbits/s; and SPAUI is a Dune-originated interface that combines the XAUI physical layer with enhancements supporting channelization and flow control similar to SPI-4.2. Each interface has the ability to run at its native speed or higher speeds, up to 6.25Gbits/s per lane. The devices feature a micro-code based parser and mapping logic, to accommodate wide range packet formats. The Petra line is designed to interoperate with an array of Packet and Networks Processors, including Marvell, EZchip, Xelerated, and Bay Microsystems, in addition to proprietary PP solutions.
The PETRA family uses external DRAM memory to buffer data. Buffering is required to enable comprehensive traffic management for carrier applications and to provide superior goodput and fairness performance.
Like previous FAP devices, the P220 and P230 interconnect and communicate via the fabric interface, enabling economic implementation of a complete product line around a single architecture. The system is scalable from 40Gbits/s to 10Tbps via mesh, single-stage configurations, and up to 100Tbps via multi-stage configurations. The backplane interface operates at rates of 6.25Gbits/s, as well as at 3.125Gbits/s for backward compatibility with previous FAP and FE devices. This enables existing systems to be upgraded in the field with denser line cards and fabric cards.
The P220 and P230 include a programmable traffic manager. The scheduling and shaping hierarchy are fully programmable, with simultaneous shaping at all levels of hierarchy. The TM is designed to be compliant with MEF and DSL-FORUM TR-059 scheduling and shaping standards, and includes additional flexibility.
EN-Genius Says…
EDITOR’S NOTE: The announcement above covers only the fabric access processor which is a companion to the FE600 Fabric Element and P130 aggregating MAC/packet pre-processor that comprise Dune’s new multi-Terabit SAND switch architecture. The review will focus on the fabric processor but we’ll try to include some information on the other devices in the family for context. For more information about these other devices please visit Dune’s web site.
Dune’s latest fabric access processors (FAPs) are scaled-up versions of the 10/20 Gbit/s FAP11V and FAP21V devices I reviewed earlier this year (see my March 2008 review) which stretches their SAND architecture comfort zone into the multi-Terabit range. As with earlier devices, the FAPs can be tied together to form relatively small fabric-less switches of up to 230 Gbit/s or combined with FE600 switch fabric for larger single- or multi-stage multi-Terabit structures. Their new 80 Gbit/s aggregating/oversubscribing MAC (the P130) rounds out the family with a compact 8X10G (or 80X1G) line interface that will make it practical for equipment manufacturers to make the shift to 10GbE with same line densities (24 - 32 lines per card) as current GbE systems.
Like Dune’s earlier fabric processors, the PETRA 220/230 handles all the tagging, segmentation, scheduling, and traffic management functions necessary to prepare packets for transport within the SAND switch fabric. As the block diagram indicates, it uses DRAM for packet buffering and faster QDR SRAM to store the packet descriptors that the ingress processor uses to perform ingress traffic shaping. Dune says it can support at least seven user-definable priority levels and can go higher if really necessary). They wouldn’t disclose the precise number of queues the processor can manage, but hinted that it’s in the 10s of thousands.
To accommodate the higher bandwidth, the processor system – side connection supports either several standard XAUI 10G interfaces or a single SPAUI connection, a hybrid of XAUI SerDes technology and SPI 4.2 channel configuration capabilities that’s supported by Bay, EZchip, and FPGA vendors plus multiple IP sources (for more information, check out the SPAUI white paper). The only important interconnect missing on this generation of Dune products is the Interlaken interface that’s being promoted by a consortium led by Cisco (see the Interlaken Alliance web site for more info). When questioned about the absence of support for Interlaken, Dune said that they see it as the most sensible choice for connections running at 40G and above. They also said that that plans are already underway to include Interlaken in future products along with SPAUI for 10G - 20G connections.
The fabric processor flexible line-side interface allows you to use whatever MAC/PHY combination you desire but Dune’s Petra P130 MAC/aggregator/traffic manager is definitely worth considering because its smart oversubscription and additional traffic management capabilities allow you to load your switch heavily and still maintain critical QoS/SLA commitments. The P130 integrated traffic manager provides buffering and contention resolution tasks at the system edge before the traffic hits the fabric processor. It goes beyond simple priority bit and VLAN tag inspection used by some MACs, allowing classification based on anything in header. This is possible thanks to the P130 packet pre-processor that uses a micro-code-based engine. The pre-processor can be programmed using a GUI-based development tool to allow support for custom applications. A typical non-standard application (if there is such a thing) would be something like prioritizing packets that are encapsulated within multiple protocols. When I asked about the aggregating MACs being sold by the likes of Marvell, Cortina, and Ample/Mindspeed, Dune said that those chips can’t match the P130 80 Gbit/s capacity and have less sophisticated classification capabilities.The FAP companion FE 600 switch fabric element (FE) has 600 Gbit/s worth of capacity and is backwards-compatible with previous FAPs, a nice feature that allows you to upgrade the switch capacity in existing equipment without the use of a forklift. Like all Dune FEs, it uses a SAR-like fabric transport mechanism that supports fixed or variable sized cell switching for improved efficiency. Instead of using external SRAM or DRAM, the FE600 uses a block of on-chip memory that eliminates the speed bump of the chip-to-chip interface. Of course such a large chunk of memory adds to the already-considerable power (Dune estimates it draws a between 25 W and 30 W) but it is acceptable for the kind of density it delivers.
All connections to the FE 600 switch are made via its 6.25 Gbit/s SerDes transceivers (5 Gbit/s useful capacity). Dune says that the transceivers have both transmit pre-emphasis and de-emphasis plus a DFE-based equalizer that allows it to accommodate nearly any channel condition in backplane environments using simple FR-4 material (not back drilled) of up to 50 inches in total length. The 3rd party IP in Dune transceivers includes a microcontroller which uses the receiver slicer circuit to implement a digital scope function that allows you to see the SerDes signal as seen at the input to the detector. This is similar to the chip-on-scope function featured in several of Vitesse’s latest offerings (see my August 2008 review) but adds the ability to automatically perform fine-tuning of equalization settings that the Vitesse parts do not have. Given the features and performance it offers, I strongly suspect that the transceiver cores are Synopsys IP (originally developed by Accelerant) but Dune would not confirm this.
Usually when a company makes claims for its new product line that are as bold as those Dune has made here, I’m more than a bit suspicious, but this looks like a logical, doable extension of their previous product lines. Based on Dune’s track record of delivering on its promises and the basic soundness of their switch architecture I think that they have a good chance at hitting their self-declared price/performance target of delivering 10GE silicon cost at around 3x the cost of 1GE silicon that they feel is necessary to drive 10GbE to mass adoption. The higher speeds, levels of integration and resulting power consumption do add some risk to the PETRA family’s successful roll-out but I’m pretty confident the have viable products that should sell well even in the weak market we’ll likely face in 2009.
Dune Networks is currently sampling the PETRA P220 and P230 to selected customers. While Dune declined to provide specific pricing for its parts, they did say that with this level of integration they expect that, in high volumes, the silicon BOM of a moderately-sized (24 - 96 port) switch should start to approach $100 per 10GE port.
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